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HP0-382 Questions and Answers
A customer has an rx7620 server with one cell. How many PCI slots are available, including the core I/O slot?
Which physical installation rule should be followed when installing several rx8620 systems at a site?
Install only one rx8620 per rack.
Install one serial console per rx8620.
Ensure that a storage array is directly beside the server.
Ensure that air ventilation is from the front of the system.
Which MP command is used to change the product number or the serial number of an rx8620 server?
What is the maximum number of PCI boards including Core I/O that can be installed on a
dual cell configuration in an rx7620 server?
On an HP Integrity rx8620 server, what happens if the system encounters a correctable L2 cache error?
The firmware logs a CMC event and reports it to the operating system.
The firmware logs an MCA event and reports it to the operating system.
The firmware deactivates the L2 cache, reports it to the operating system and an entry is created in the PDT.
Since it is a correctable error, no action is taken immediately. On the next reboot, the user should deallocate the CPU at EFI level.
What is "cell-local memory" (CLM)?
memory installed and configured on one hard partition so that only cells from that hard partition can use it
memory dedicated to the CPUs on the same cell where it is installed, so that CPUs from other cells cannot access this memory
virtual memory created by the operating system's kernel to allow processes to be executed on a cell, instead of on a hard partition
a memory topology derived from "interleaved memory" with extra features such as "cell
local online memory replacement and addition" and "cell-local RAID0+1 topology"
What does chip spare/kill accomplish on the rx7620 server?
When the memory has a double-bit error, OpenVMS will keep running by sparing the bad chip immediately.
When the memory has a double-bit error, HP-UX will keep running by sparing the suspect bad chip immediately.
When a complete chip failure causes single-bit errors that are covered by the hardware/firmware, chip spare keeps the system running.
When the memory has one single-bit error, Linux will panic. However, on reboot the
hardware/firmware does a chip spare at the next boot.
When comparing Pentium processor-based servers with Itanium processor-based servers such as the HP rx7620/rx8620, what does Extensible Firmware Interface (EFI) replace?
Non Volatile RAM (NVRAM)
Basic Input Output System (BIOS)
Advanced Configuration and Power Interface (ACPI)
Advanced Programmable Interrupt Controller (APIC)
What is the key difference between SRAM and DRAM?
DRAM is faster because it is dynamic.
SRAM means Speed RAM and is faster.
SRAM is faster because it is synchronous.
DRAM is faster because it uses dual inline technology.
What is the maximum number of echelons supported per cell on the rx7620 server?
Which statement is correct regarding multi-level caching?
If the larger cache misses, the next smaller cache is checked.
Level 4 caching is usually the fastest resource for the processor.
Multi-level caches generally operate by checking the largest level cache first.
Multi-level caches generally operate by checking the smallest level 1 cache first.