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C4040-252 - Power Systems with POWER8 Enterprise Technical Sales Skills V1 - Dump Information

Vendor : IBM
Exam Code : C4040-252
Exam Name : Power Systems with POWER8 Enterprise Technical Sales Skills V1
Questions and Answers : 85 Q & A
Updated On : April 19, 2018
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C4040-252 Questions and Answers

C4040-252 Power Systems with POWER8 Enterprise Technical Sales Skills V1

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C4040-252 Certification Brain Dumps Source : Power Systems with POWER8 Enterprise Technical Sales Skills V1

Test Code : C4040-252
Test Name : Power Systems with POWER8 Enterprise Technical Sales Skills V1
Vendor Name : IBM
Q&A : 85 Brain Dump Questions

IBM Power Systems with

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March 26, 2018 Timothy Prickett Morgan

The hole between what most IBM i consumers want from vigour systems hardware – exceptionally when it comes to compute skill – and what huge Blue can deliver has been widening for the reason that concerning the Power7 technology back in 2010. but, thanks in colossal measure to the decelerate in Moore’s legislation advances in chip manufacturing processes, the gap is going to beginning closing. not so tons as a result of IBM wants it to, however quite because of the boundaries of physics.

And, considering the IBM i platform is a database platform that primarily does transaction processing and analytics, IBM’s shift faraway from compute and towards memory and i/O enhancements that engender every kind of acceleration the usage of GPUs, FPGAs, and non-unstable reminiscence is a pretty good thing . . . . in theory. In apply, besides the fact that such acceleration has been around for years now and is a key strategic factor of the vigor methods – excuse me, the Cognitive techniques – platform, IBM has no longer in reality leveraged GPU and FPGA acceleration for IBM i workloads. The enterprise has finished a pretty good job in advertising using flash memory to speed up storage, and it has moved to usual DRAM as opposed to its personal “Centaur” buffered DRAM to decrease the can charge of main memory on entry Power9 techniques. The combination of higher and more cost-effective leading reminiscence, flash storage, and ample compute will meet the existing needs of most IBM i retail outlets within a two-socket server form aspect.

however we want to look forward, and to look the broader spectrum of workloads that may – and will – be operating at IBM i shops. large Blue goes to the entire difficulty to rebrand the Db2 for IBM i database, however it doesn’t basically do the rest to modernize it, to accelerate it like crazy, so it cannot simplest do more work quicker, however also to do distinctive kinds of work equivalent to superior analytics and computer getting to know. it is with this in intellect that we now have mentioned acceleration in the past, and the way IBM may create something we have referred to as the Cognitive systems/500, a gadget (not only a desktop) very a great deal like the Power9-based mostly AC922 device that IBM launched last December and that is the company’s flagship equipment for AI and HPC workloads. (that you could see our preliminary insurance on the Power9 architecture here, which is effective for the functions of this dialog.)

IBM hosted its think 2018 company companion and customer conference last week in Las Vegas, and at the same time, the business’s partners additionally had their personal shindig at the OpenPower Summit; this turned into additionally the equal time that facebook was conserving its own Open Compute Summit, so it changed into a busy week in infrastructure. IBM did lots of talking about the brilliant new Power9 programs and its equipment z14 mainframes closing week, as you might imagine, and admittedly, we told you greater about the Power9 “ZZ” entry systems in the past few weeks than you might gain knowledge of at believe 2018. Which means we're doing our jobs, we think. however the new thing that did come out of the OpenPower Summit was an up-to-date energy processor roadmap, which Brad McCredie, the founding president of the OpenPower basis, an IBM Fellow, and vice chairman of Cognitive systems construction at IBM, talked a bit about.

Let’s take a look at this roadmap:

The shift from specializing in compute to focusing in I/O started with the Power8+ chip, a name which IBM stopped the use of because it wanted to emphasize the proven fact that, youngsters there were some microarchitecture improvements with this chip, the big trade was not the rest having to do with CPU cores or caches, but somewhat the combination of the NVLink 1.0 interconnect, which allows for for the “Pascal” P100 Tesla GPU accelerators from Nvidia to be tightly coupled with each other and with the Power8+ processors from IBM. This chip become definitely the proof of idea for the Power9 chip that became launched late ultimate 12 months and that we've been speakme about for years now with exquisite anticipation.

As which you can see, IBM has taken its personal tick-tock approach to updating the energy chip household, but no longer on rather the equal tight schedule and never in precisely the same method as Intel. With the Intel tick-tock formulation, the tick is a transformation in manufacturing process, say a decrease from forty five nanometer chip etching suggestions to 32 nanometer methods, while the tock is a transformation in architecture, akin to core design, adjustments in cache hierarchy, and the addition of accelerators. To mitigate its possibility, Intel tried not to do a system change and an structure alternate on the same time. Too many things can go wrong. at the moment, as Moore’s law improvements in manufacturing processes are becoming harder to come back through, Intel has shifted to a 3 step process we now have called tick-tock-clock, which skill there's a third step now where a process is extra refined and performance enhancements come out with a 3rd technology as opposed to moving on to a subsequent generation. There just aren't that many steps left after 14 nanometers before we will hit the boundaries of transistor physics, starting with 10 nanometers followed perhaps with the aid of 7 nanometers and then through 5 nanometers and maybe right down to three nanometers, supply or take a nanometer here or there. There may well be best 7 nanometers down to 4 nanometers because the fundamental steps beyond 10 nanometers. After that, you're right down to etching with individual atoms, and that's just now not going to work from a physics or economics standpoint.

With the Power7 chips in 2010, IBM did eight cores in 45 nanometers, and then with the Power7+ chip two years later, massive Blue tweaked the microarchitecture slightly while moving to a tons smaller 32 nanometer technique, nevertheless it used that cut back to decrease manufacturing expenses and didn't raise the core count number. The Power8 in 2014 now not most effective did a procedure decrease to 22 nanometers, however also did a substantial reworking of the vigor cores while at the same time boosting the core count by way of 50 % to 12 cores per chip. IBM had versions of the Power8 with six cores and put two of them in a single kit to create sockets with 12 cores whereas at the identical time it also created models of the Power8 chip with all 12 cores on a single die, which can be extra expensive. The Power8 chips could use either DDR3 or DDR3 reminiscence, and included eight reminiscence controllers on the die, enabling for a factor of 3.2X enhance in reminiscence bandwidth over the Power7 and Power7+ chips. The Power8 chip from 2014 additionally used PCI-specific three.0 peripheral slots, and allowed the initial CAPI 1.0 protocol for coherently attaching accelerators to the vigor reminiscence complex to run atop the PCI-specific ports. With the Power8+ chip two years later, IBM introduced 20 Gb/sec signaling on its prototype “Bluelink” prevalent, high velocity I/O ports, and these new I/O lanes were used to create 4 ports with 20 Gb/sec of bandwidth in each and every route to make the NVLink 1.0 ports for hooking four Pascal P100 accelerators to the Power8+ CPU, with a rudimentary cache coherency throughout the CPUs and GPUs.

With the Power9 “Nimbus” and “LaGrange” scale-out Power9 chips, which can be shipping within the AC922 and ZZ methods that IBM has already introduced, a couple of different things came about. IBM shifted to a 14 nanometer procedure at its associate, GlobalFoundries, which bought the IBM Microelectronics company four years ago. This system decrease allowed IBM to cram as much as 24 skinny cores with SMT4 threading (four threads per core) or 12 fat cores with SMT8 threading (eight threads per core) on a single die. definitely, IBM allowed the cores to be cut in half and the threading degree to be reduce in half compared to the Power8 chips if it's how clients wish to dice and slice the compute, however really, the core count did not go up within the strictest experience. (12 cores with SMT8 is what the Power8 and Power8 supported, and here is additionally all that the Power9 supports.)

For the entry Power9 machines, IBM also wanted to get its memory charges down, so it shifted away from its personal Centaur buffered memory and L4 cache and to straightforward vanilla DDR4 main reminiscence. There are nonetheless eight reminiscence controllers on the Power9 SO die, however devoid of the buffers the sustained reminiscence bandwidth drops by using 29 %, from 210 GB/sec per socket with the Power8 and Power8+ to one hundred fifty GB/sec for the Power9 SO variants. also with the Power9 SO chips, IBM is boosting the Bluelink lane velocity to 25 Gb/sec, which is pretty much as good as latest Ethernet swap chips can do, which across six NVLink ports on the Power9 SO processor ability it might present 300 GB/sec of bandwidth. The shift to 48 lanes of PCI-express 4.0 peripheral I/O doubles the bandwidth for other peripherals. The OpenCAPI three.0 protocol runs on the Bluelink lanes – they don’t should guide NVLink 2.0 solely – and the up-to-date CAPI 2.0 protocol can run atop PCI-specific 4.0.

With the “Cumulus” Power9 chips used in the future scale up variations of vigour systems with 4, eight, 12, or sixteen sockets in a single device picture, IBM will retain the Centaur DDR4 buffered memory and the sustained reminiscence bandwidth will reside the same at 210 GB/sec per socket. The chart implies that there might be versions accessible with 24 skinny cores sporting SMT4 threading, however so far as we understand, IBM most effective plans to offer 12 fat cores with SMT8 threading in these machines. additionally, the chart implies that the bandwidth on the Bluelink ports will dwell the same, but some of these Bluelink ports are going to be used up in creating the NUMA shared reminiscence throughout sockets, as we now have mentioned in our evaluation of the future “Fleetwood” sixteen-socket vigour E980 system that will come out within the third quarter. there will still be some Bluelink ports left over to run OpenCAPI or NVLink ports for those who are looking to try this for hooking in GPU, FPGA, or flash accelerators.

That brings us to the Power9+ kickers due beginning in 2019, to be able to have the identical core counts as the Power9 versions and be applied in an better 14 nanometer method from GlobalFoundries. while there may be some microarchitecture advancements with these Power9+ chips, there will not be a substantial trade in performance, we are guessing, at the least now not in the core compute complicated. however there should be enhancements in the memory subsystem and within the protocols working on the I/O subsystem with a view to allow these cores to be superior fed with records and therefore get greater work finished on the compute means that's there. this is additionally a form of efficiency improvement.

The PCI-specific 4.0 and Bluelink I/O subsystems could be the identical on this future Power9+ family unit of chips when it comes to the signaling costs and peak and sustained bandwidths. however the CAPI, OpenCAPI, and NVLink protocols will all be updated to run better. IBM is additionally shifting to a brand new reminiscence subsystem, and McCredie offered some tips on the way it could be performed in this slide:

If this chart is to be taken actually, the Bluelink ports are proven on the southbound I/O coming off the vigour compute complex, making OpenCAPI and NVLink ports as we know they do. however this also indicates Bluelink ports going northbound, as much as JEDEC-compliant memory buffers. We suspect that this could be for DDR4 or DDR5 DRAM memory, but it surely may even be for persistent non-volatile storage, similar to ReRAM or 3D XPoint, which is additionally bit addressable like DRAM.

If we were IBM, we could preview Bluelink-attached DDR4 DRAM, with reminiscence buffers sitting between the compute complex and the DRAM, in these Power9+ chips. To get the 67 p.c raise in memory bandwidth shown with the Power9+ chips, the number of memory controllers can be pushed up through 50 percent to a dozen per die and the variety of memory slots could be extended by means of a factor of fifty percent as neatly, to 48 sticks per socket with buffers or 24 sticks with out them. in case you raise the reminiscence speed to three.eight GHz from the existing 3.2 GHz when the entire slots are occupied as is the case with the Power9 ZZ machines, that you may get that bandwidth. this is simply conjecture, of path. The DDR5 specification can be executed this 12 months, and for all we recognize, IBM will do anything like this with early and geared down DDR5 reminiscence sticks. DDR5 memory will present twice the capability and twice the bandwidth of DDR4 when it does arrive.

We suppose that IBM will raise the memory slots with the Power9+ chips is a cease-gap maneuver because big Blue has to stay up for DDR5 unless the Power10 chips come out in 2020 or 2021, and furthermore that it is hedging its bets right here during this energy roadmap. however we consider the Power10 can be designed to have a a great deal greater bendy memory subsystem underpinned by using 50 Gb/sec Bluelink signaling and that it's going to additionally help 32 Gb/sec Bluelink signaling for different features of the device. (The chart suggests that these two speeds will be attainable.) by means of relocating to DDR5 with the Power10, it could be able to drop the variety of reminiscence slots lower back down to 32 with buffers and 16 without buffers while boosting the pace a little to three.four GHz on the memory to reach that 435 GB/sec of leading memory bandwidth shown in the chart.

The Power10 chip will additionally support PCI-categorical 5.0 peripherals, which once again will double up the I/O bandwidth in comparison to PCI-express four.0. The number of cores has yet to be determined with the Power10 chip, and that's because the world’s important HPC and AI centers have not figured out what they could want three years from now. We think it is extremely unlikely that IBM will do greater than a 50 p.c increase to 36 skinny cores with SMT4 or 18 fats cores with SMT8. We also doubt it is going to retain the core count the equal if the chips are implemented within the 7 nanometer strategies from GlobalFoundries, as we suspect they may be. GlobalFoundries, incidentally, is itself hedging on its 7 nanometer manufacturing strategies in the Malta, big apple fab. it'll have common immersion lithography with 7 nanometers in addition to its first run of severe ultraviolet lithography at 7 nanometers. So IBM may have two the right way to get there, one potentially much less harmful however the different with a lot fewer manufacturing steps and complexity and for this reason at a lessen cost.

The task now's to get IBM to really redecorate the IBM i software stack, and a variety of Linux functions that may run along side IBM i, to take full abilities of those capabilities. green reveal functions with even the worst viable screen scrapers cannot even dent this form of compute and i/O, and disk arrays can’t contact it, either. imagine a two-socket equipment with 72 cores, many terabytes of main reminiscence and tens of terabytes of addressable non-volatile storage, and petabytes to tens of petabytes of flash storage, with a terabyte per 2d of bandwidth within the device bus and maybe two or three times that of combination reminiscence and that i/O bandwidth piping into the compute complex. it's time for IBM i to go HPC and AI.

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Cirrascale Cloud functions Expands choices to include IBM POWER9 programs with NVIDIA Tesla V100 GPUs | killexams.com real questions with brain dumps

SAN JOSE, Calif., March 28, 2018 — Cirrascale Cloud features, a premier provider of multi-GPU deep getting to know cloud options, today introduced the availability of the IBM energy programs AC922 on its deep studying and HPC cloud platform. numerous configurations will support POWER9 processors with up to 20-cores and up to four NVIDIA Tesla V100 GPUs with Volta structure the use of NVIDIA NVLink, a excessive-pace bidirectional interconnect.

The IBM vigor systems AC922 is an entire redesign aiding the latest applied sciences including CAPI 2.0, PCIe Gen four, in addition to NVLink 2.0 which is embedded at the silicon level and tightly coupled with the CPU. This enables up to 150GB/sec of bi-directional bandwidth for statistics-intensive workloads, essentially 5X the CPU:GPU bandwidth of PCIe. every GPU is serviced with 300GB/sec of NVLink bandwidth, practically 10X the records throughput of PCIe x16 three.0 platforms. additionally, consumers will note reduced latencies with memory and NVMe gadgets. normal, these optimizations accelerate deep learning and HPC workloads similar to weather modeling, self sufficient transportation, herbal language processing, and speech cognizance.

Cirrascale Cloud functions differentiates its platform by using offering the trade’s most up-to-date, dedicated GPUs as a bare metal providing. This gives users the entire power of contemporary, dedicated, directly attainable GPUs and associated compute hardware, as well as most desirable flexibility in system configuration. The purchasable configurations make certain that a large choice of application forms can also be addressed including deep getting to know, synthetic intelligence, high performance statistics analytics, and accelerated databases.

“Deep discovering and HPC workloads require an advanced level of computing structure between CPUs and GPUs to get to the bottom of bandwidth bottlenecks,” observed Mike LaPan, vice chairman, Cirrascale Cloud features. “With the Cirrascale Cloud features platform providing the brand new IBM POWER9 servers, consumers can experience the subsequent stage of GPU-accelerated computing across industries.”

POWER9 configurations are available automatically with support for the newest GPUs from NVIDIA, such as the Tesla V100 GPU. customers drawn to these and other configurations can discuss with http://www.cirrascale.cloud to sign in or contact Cirrascale Cloud capabilities at (888) 942-3800.

About Cirrascale Cloud functions

Cirrascale Cloud services is a premier company of public and private dedicated, multi-GPU cloud solutions enabling deep learning. The enterprise presents cloud-primarily based options for significant-scale deep researching operators, carrier suppliers, in addition to HPC clients. To be trained extra about Cirrascale Cloud functions and its entertaining committed, multi-GPU cloud options, please consult with http://www.cirrascale.cloud or name (888) 942-3800.

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C4040-252 Power Systems with POWER8 Enterprise Technical Sales Skills V1

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C4040-252 Certification Brain Dumps Source : Power Systems with POWER8 Enterprise Technical Sales Skills V1

Test Code : C4040-252
Test Name : Power Systems with POWER8 Enterprise Technical Sales Skills V1
Vendor Name : IBM
Q&A : 85 Brain Dump Questions

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IBM C4040-252 Exam (Power Systems with POWER8 Enterprise Technical Sales Skills V1) Detailed Information



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